UVM
书籍推荐
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SystemVerilog验证,第二版
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UVM实战,张强
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芯片验证漫游指南,刘斌
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The UVM Primer
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Pratical UVM step by step examples
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A Prtical Guide to Adopting the universal verification methodology (UVM) second edition
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ASIC/SOC functional design verification
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systemverilog assertions and functional coverage
学习资源
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首推“验证学院”,由Mentor编写,有Cookbook,有视频教程。
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“验证指导”,包括SystemVerilog教程、UVM教程、SystemC教程等。
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“ASIC World”的SV教程,据说这个网站每月有超过3百万的浏览量。
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doulos教程
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UVM candy lovers 教程
http://cluelogic.com/category/uvm/
http://cluelogic.com/2011/07/uvm-tutorial-for-candy-lovers-overview/
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chipverify
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uvm tutorial
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UVM教程
UVM仿真参数
UVM Compile options
- +UVM_REPORT_DISABLE_FILE
- +UVM_REPORT_DISABLE_LINE
- +UVM_REPORT_DISABLE_FILE_LINE
UVM runtime options
- +UVM_TESTNAME :
- +UVM_VERBOSITY : allows the user to specify the initial verbosity for all components
- +UVM_TIMEOUT : allows users to change the global timeout of the UVM framework
- +UVM_MAX_QUIT_COUNT : allows users to change max quit count for the report server
- +UVM_CONFIG_DB_TRACE : turns on tracing of configuration DB access
- +UVM_DUMP_CMDLINE_ARGS
- +UVM_OBJECTION_TRACE : turns on tracing of objection activity
- +UVM_PHASE_TRACE : turns on tracing of phase executions
- +UVM_RESOURCE_DB_TRACE : turns on tracing of resource DB access
- +uvm_set_config_int
- +uvm_set_config_string
- +uvm_set_inst_override
- +uvm_set_type_override
- +uvm_set_verbosity +uvm_set_verbosity=,,, and +uvm_set_verbosity=,,,time, allow the users to manipulate the verbosity of specific components at specific phases
- +uvm_set_action
- +uvm_set_severity